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swscale/aarch64/rasm: add blr instruction

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And a64op_lr() helper for LR register.

Sponsored-by: Sovereign Tech Fund
Signed-off-by: Ramiro Polla <ramiro.polla@gmail.com>
This commit is contained in:
Ramiro Polla
2026-06-10 01:46:29 +02:00
parent ecba7e1d42
commit 061dc9ab6d
2 changed files with 4 additions and 0 deletions
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libswscale/aarch64/rasm.h
+3
View File
@@ -249,6 +249,7 @@ typedef enum AArch64InsnId {
AARCH64_INSN_AND,
AARCH64_INSN_B,
AARCH64_INSN_BCOND,
AARCH64_INSN_BLR,
AARCH64_INSN_BR,
AARCH64_INSN_CMP,
AARCH64_INSN_CSEL,
@@ -351,6 +352,7 @@ static inline uint8_t a64op_gpr_size(RasmOp op) { return op.u8[1]; }
static inline RasmOp a64op_gpw(uint8_t n) { return a64op_make_gpr(n, sizeof(uint32_t)); }
static inline RasmOp a64op_gpx(uint8_t n) { return a64op_make_gpr(n, sizeof(uint64_t)); }
static inline RasmOp a64op_lr (void) { return a64op_make_gpr(30, sizeof(uint64_t)); }
static inline RasmOp a64op_sp (void) { return a64op_make_gpr(31, sizeof(uint64_t)); }
/* modifiers */
@@ -540,6 +542,7 @@ static inline RasmOp a64cond_nv(void) { return a64op_cond(AARCH64_COND_NV); }
#define i_and(rctx, op0, op1, op2 ) rasm_add_insn(rctx, AARCH64_INSN_AND, op0, op1, op2, OPN)
#define i_b(rctx, op0 ) rasm_add_insn(rctx, AARCH64_INSN_B, op0, OPN, OPN, OPN)
#define i_bcond(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_BCOND, op0, op1, OPN, OPN)
#define i_blr(rctx, op0 ) rasm_add_insn(rctx, AARCH64_INSN_BLR, op0, OPN, OPN, OPN)
#define i_br(rctx, op0 ) rasm_add_insn(rctx, AARCH64_INSN_BR, op0, OPN, OPN, OPN)
#define i_cmp(rctx, op0, op1 ) rasm_add_insn(rctx, AARCH64_INSN_CMP, op0, op1, OPN, OPN)
#define i_csel(rctx, op0, op1, op2, op3) rasm_add_insn(rctx, AARCH64_INSN_CSEL, op0, op1, op2, op3)
libswscale/aarch64/rasm_print.c
+1
View File
@@ -272,6 +272,7 @@ static const char insn_names[AARCH64_INSN_NB][8] = {
[AARCH64_INSN_AND ] = "and",
[AARCH64_INSN_B ] = "b",
[AARCH64_INSN_BCOND ] = "b",
[AARCH64_INSN_BLR ] = "blr",
[AARCH64_INSN_BR ] = "br",
[AARCH64_INSN_CMP ] = "cmp",
[AARCH64_INSN_CSEL ] = "csel",